1. Field of the Invention
This invention relates to the formation of contact holes, vias and trenches in semiconductor devices. More particularly, the present invention relates to methods and devices for determining and/or identifying defects in processes for forming contact holes, vias or trenches in layers of integrated circuits.
2. Description of the Related Art
The fabrication of semiconductor devices often requires the formation of contact holes, vias and/or trenches to electrically interconnect different layers of semiconductor devices or to interconnect a layer to an underlying substrate. Such contact holes, vias and trenches may be filled with an electrically (semi)conducting material such as, for example, metal (e.g., aluminum, tungsten, copper, etc.) to electrically interconnect metalization layers or to electrically connect such a layer to the substrate. The proper formation of such contact holes, vias and trenches, therefore, is essential for the formation of good electrical interconnects. Faulty contact holes, vias and trenches may be formed by, for example, phenomena such as silicon "grass", for example, wherein spike and spire-like structures remain at the bottom of the contact hole after the contact-forming etch step. Other causes of such faulty contact holes are believed to be related to stepper focus issues, film voids and uniformity problems that change the etch rate and that lead to malformed or missing contact holes, blocked nitride etches and etcher temperature control problems that lead to a non-uniform etch rates and/or polymer build-up problems, to name a few common causes.
The quality of deep (high aspect ratio) sub-micron contact holes is critical to the yield of the underlying process. Indeed, using 0.25-micron technology, for example, a typical die may contain in excess of 10 million contact holes. It is, therefore, essential to ensure that the process steps employed to create such contact holes are optimized and create good electrical contacts between the appropriate layers.
A conventional method of validating the presence and electrical functionality of the contact holes is to fully complete the IC manufacturing process and then to perform conventional electrical testing to determine bit failures. However, such conventional electrical testing does not necessarily test or analyze all contact holes for electrical conductivity. Moreover, the time necessary to complete the manufacturing process and to electrically test the devices is often on the order of about three to four weeks. Thereafter, should process parameters require adjustments because of an unacceptably high bit failure rate, for example, this manufacturing, test and defect analysis cycle must be repeated, consuming another three to four weeks, leading to delays in bringing new products to market and competitive disadvantage. These delays are onerous, therefore, not only in terms of the time necessary to validate the process parameters, but also in terms of the high costs associated with such manufacturing and extended testing cycles.
Conventionally, to properly diagnose the underlying cause of the detected bit failures, it has been necessary to employ, for example, Scanning Electron Microscopy (hereafter "SEM") or Tunneling Electron Microscopy (hereafter "TEM") to accurately visualize the bottom of the via, contact hole, trench or other high aspect ratio structure. Such devices, although effective in resolving most defect structures at the bottom of such contact holes, are slow and expensive, costing on the order of about $10 million apiece.
Clearly, there has been a long felt need for devices and methods to detect and analyze such contact holes, vias and trenches that do not occasion such large expenditures of time and money. For such methods and devices to be effective, however, they should be able to measure all types of contact holes to silicon (and optionally, to a local interconnect structure and/or metallization layer other than the uppermost metal layer) and cover the entire wafer (or alternatively, a statistically significant percentage of and/or number of locations on a wafer). The current alternatives to SEM or TEM-based instruments include conventional optical wafer defect inspection tools, such as the ILM-2230, or KLA.RTM.-2132 or 2138 wafer inspection tools commercially available from KLA-Tencor Corporation, San Jose, Calif., or such tools as the WF-700 Series Wafer Defect Inspection System commercially available from Applied Materials of Santa Clara, Calif. However, such tools typically detect defects only at the surface of the integrated circuit topography. The high aspect ratio of typical contact holes, vias and/or trenches forecloses the use of such tools, as such wafer surface inspection devices typically lack the depth of focus necessary to resolve the bottom of the contact hole, via and/or trench. To allow such a wafer surface inspection tool to visualize the bottom of such structures, the surrounding structures and/or topography (herein, "topography" generally refers to structures formed on the integrated circuit ["IC"]) must be somehow removed for the tool to visualize the silicon substrate. This has conventionally been difficult, since polysilicon is often used as part of the product wafer topography. Any method used to remove the polysilicon would also remove any exposed silicon substrate and negatively affect the silicon substrate.
An example of one of the common problems encountered in defining the process parameters for creating a clean contact in a semiconductor device is shown in FIG. 1. In the illustrative example shown in FIG. 1, each of the gate structures includes a polysilicon layer 120 and a tetraethyl orthosilicate (hereafter "TEOS") layer 110. Protecting and isolating each of the gate structures is a pair of sidewall spacers 130, which may also be formed of TEOS. Encapsulating the gate and sidewall structures is a silicon nitride layer 140. Formed on the nitride layer 140 is a layer of boron and/or phosphorous-doped oxide, such as borophosphosilicate glass (hereafter "BPSG"). A capping layer of silicon dioxide 180 formed from, for example, TEOS, is deposited on the BPSG 170. After deposition and patterning of a photoresist layer (not shown), an etching step is carried out to form the self-aligned contact hole 160. As shown at reference numeral 165 in FIG. 1, so-called "grass" 165 may remain at the bottom of the contact hole 160, thereby preventing a good electrical contact between the metal layer to be deposited in the contact hole 160 and the underlying silicon substrate 150. The "grass" 165 may be formed of, for example, an insufficiently or non-uniformly etched nitride layer 140 and/or BPSG residue. Such structural defects adversely affect the performance of the resultant device and decrease the overall fabrication yield for that wafer. Similar defects may arise in processes for forming vias and/or trenches. Conventionally, the only way to detect such unwanted "grass" and other unwanted structural malformations was to infer its existence from the results of the electrical conductivity tests and/or to employ expensive and time consuming visualization instruments, such as SEM or TEM-based devices.
What are needed, therefore, are methods and devices to determine and/or identify defects in a process for forming a contact hole, via or trench in a layer of an integrated circuit. What are also needed are devices and methods to validate the integrity of such contact holes, vias and/or trenches that do not depend upon expensive and slow electron microscopy devices and techniques. It is also believed that there has been a long felt need for methods and devices that would allow faster and relatively inexpensive wafer inspection tools to be used to inspect the bottom of such high aspect ratio contact holes, vias and/or trenches, notwithstanding the inherent depth of focus limitations of such devices.